1. Field
The present disclosure relates to the assembly of device and integrated circuit components on a substrate to provide hybrid electronic, optoelectronic, or other types of integrated electronic systems. For example, the present disclosure describes a method for fabricating arbitrarily configured arrays of devices or components on host circuits or substrates with a specific orientation using fluid-based transport or other mass dispersing techniques.
2. Description of Related Art
Increasingly complex integrated electronic and optoelectronic systems require larger numbers of integrated circuits and devices to implement increasingly complex system functions. However, to achieve cost and weight goals, it is preferred that these integrated systems be implemented with as few separate device structures as possible. One approach is to fabricate all of the integrated circuits and devices on a single wafer or portion of a wafer, which provides the structural base for the system and minimizes the interconnect distances between circuits and devices. Such fabrication may be referred to as “wafer-scale” integration.
Many complex integrated electronic and optoelectronic systems require the use of integrated circuits and devices that utilize different semiconductor technologies. One approach known in the art for wafer-scale integration of different semiconductor technologies is heteroepitaxy. The heteroepitaxy approach may limit the number of different devices and material systems that can be successfully integrated. Moreover, growth and fabrication procedures optimized for a single device technology often must be compromised to accommodate dissimilar material systems. Finally, testing of individual portions of the integrated system may be made difficult by the fabrication techniques used to accommodate dissimilar material systems on a single wafer.
Since it may be difficult to fabricate high performance systems using multiple device types using heteroepitaxy approaches, it may be preferable to fabricate separate arrays of devices or circuit modules and couple these separately fabricated components to a host wafer. This approach allows each individual component to have state-of-the-art performance and high yield (due to pre-testing). Each component may use proven device and circuit architectures, while optimum epitaxial growth and/or device processing sequences are employed to fabricate each component.
The separate components may be individually integrated with the host wafer using any one of several established methods for chip-level integration. These methods generally rely upon surface-mounting techniques for attaching complete die assemblies using solder bumps or wire bonding. The most advanced of these methods is the “flip-chip” technique that can support integration of a wide variety of device technologies and fully utilizes the costly, high-performance device wafer real estate. However, flip-chip is generally limited to relatively large size components, typically greater than 1 square millimeter, and is inefficient for the placement of large numbers of components due to its serial nature.
At the wafer-scale level, self-assembly methods provide the best capability to allow integration of arbitrary configurations and densities of components. The most advanced of the self-assembly methods use a fluid medium to transport components to a host substrate or wafer for assembly. Two different fluidic self-assembly methods are known in the art, which differ in the underlying mechanism used to locate, position, and connect the components on the host substrate or wafer.
The first method of fluidic self-assembly uses gravitational forces and geometrical constraints to integrate components with a host substrate. The components are fabricated with specific shapes and complementary shaped receptacles are formed on the substrate for receiving the shaped components. The components are typically formed using semiconductor fabrication techniques and the receptacles are formed by using wet or dry etching techniques. A solvent such as water or ethanol is used to transport the individual components to the host substrate with the receptacles. The receptacles trap the components, which come to rest in predictable orientations due to their specific shapes. The driving potential is primarily gravitational in origin, but the fluid and surface forces may also play a role in the assembly process.
The second method of fluidic self-assembly utilizes chemically-based driving forces to govern the assembly process, where the attraction, positioning, orientation, and ordering of components is controlled by molecular interactions at the surfaces of the components and the host substrate. Molecular-based self-assembly techniques generally use surface coatings that consist of chemically-bonded films which are either hydrophobic or hydrophilic by nature. Thermodynamic driving forces control the assembly of complex arrays of components by minimizing the surface energies of the components and host substrate.
Both methods may be used together to provide for integration of electronic and opto-electronic devices into hybrid electronic systems. See, for example, A. Terfort, et al., “Self-Assembly of an Operating Electrical Circuit Based on Shape Complementarity and the Hydrophobic Effect,” Adv. Material, 10, No. 6, 1998, pp. 470–473. See also A. Terfort, et al., “Three-dimensional Self-Assembly of Millimeter-scale Components,” Nature, Vol. 386, Mar. 13, 1997, pp. 162–164.
Methods for fabricating device microstructures by fluidic self-assembly have also been the subject of various U.S. patent disclosures. For example, U.S. Pat. No. 5,545,291, which is incorporated herein by reference in its entirety, describes one such method comprising the steps of providing a plurality of shaped blocks, each shaped block comprising an integrated circuit thereon; transferring said shaped blocks into a fluid to form a slurry, and dispensing said slurry over a substrate at a rate where at least one of said shaped blocks is disposed into a recessed region in the substrate. In the '291 patent, the substrate is selected from a group consisting of a silicon wafer, plastic sheet, gallium arsenide wafer, glass substrate, and ceramic substrate. The flow is substantially a laminar flow and the rate of flow allows each of the shaped blocks to self-align into the recessed region.
In the '291 patent, the blocks comprising the integrated circuit device thereon are shaped by masking and etching. Referring to FIGS. 1 to 3 of the attached drawings, a block substrate 2 is provided with a top layer, a bottom layer 6 and a sacrificial layer 8 atop the top surface of the bottom layer 6 (see FIG. 1). The blocks are shaped by masking and etching the top layer using known techniques to form the etched block substrate shown in FIG. 2 comprising photoresist layer 10 atop shaped blocks 12. Then the shaded blocks 12 are removed by preferential etching of sacrificial layer 8 (see FIG. 3). The removed blocks 12 (see FIG. 3) are then mixed with an inert fluid to form a slurry and the slurry is deposited on the top surface of a substrate comprising recessed regions to allow the blocks to self-align in the recessed regions of the substrate.
To insure proper placement and registration of the microstructures in the recessed regions, the recessed regions in the prior art substrates have been etched to provide receptacle sites with geometric profiles that are complementary to the profiles of the blocks. Receptacle sites in other reports of fluidic self-assembly have also been made by etching recesses in the surface of silicon substrates. Single crystalline silicon can be etched by a number of methods to produce a variety of sidewall profiles. The etching behavior of most wet-processes can be categorized as isotropic or crystallographic. Receptacles fabricated using crystallographic etches are the most favorable for forming receptacle sites.
Crystallographically etched receptacles in a silicon substrate have been obtained by using an aqueous potassium hydroxide (KOH) solution. It is difficult to produce complementary shapes between receptacles and device microstructures using KOH etch techniques, because the microstructures require an exterior surface etch and the receptacles require an interior surface etch. The best results for shape matching have been achieved using corner compensation masking techniques for etching the device microstructure. These techniques prevent the corners from being rounded. However, in general, the microstructures are found to be etched with a more tapered shape than the receptacle sites. This leads to a loose fit.
A layer of polymer material may be used as the substrate in which receptacles are formed. The receptacles in the polymer material may be formed using plasma etching. Methods for forming tapered holes in polyimide are well-known in the art. The methods for forming tapered sidewalls typically involve using specially prepared photoresist masks (tapered erosion masks). These methods are typically limited to several microns of depth because the masking material and the polymer etch at the same rate.
Another method for forming receptacles in polymer material is disclosed in the commonly assigned and copending application “Method For Assembly of Complementary-Shaped Receptacle Site and Device Microstructures,” U.S. application Ser. No. 10/218,052. This application describes a method for forming receptacles by first creating a mold having a protuberance with the same shape as a protuberance on a device microstructure. The mold is then applied to a moldable substrate, typically a polymer material, to form a receptacle site having a complementary shape to the protuberance on the device microstructure. Fluidic self-assembly is then used to provide the device microstructure to the molded substrate, and the device microstructure then self-aligns in the recess. Typically, the mold will have multiple protuberances so that multiple recesses will be formed in the moldable substrate when molded with the mold.
The three dimensional shapes of the shaped blocks comprising the microstructures or parts thereof and the complementarily-shaped receptacles described in the prior art are generally invariant under 360 degree rotation. That is, the shapes generally have no specific orientation in the plane defined by the surface containing the receptacles. Hence, when the microstructures are positioned within the receptacles, the microstructures may be oriented within the receptacle in any one of several orientations defined by the receptacle shape. For example, a receptacle having a square shape, that is, a shape with four equal length sidewalls, would allow a microstructure to be positioned in any one of four different orientations. Variations in the orientations of the microstructures positioned within the receptacles complicates the steps needed to make electrical, optical, or other types of connections to the microstructures. The variations in the orientations may also limit or complicate the electrical or optical designs implemented by the microstructures.
The three-dimensional shapes of the shaped blocks comprising the microstructures or portions thereof and the complementarily shaped receptacles may also hinder the self-alignment capabilities of the microstructures. Due to these shapes, a microstructure may be introduced in a skewed fashion to the corresponding receptacle, causing the microstructure to become stuck in the receptacle, but not properly seated in the receptacle. Those skilled in the art will understand that this problem is more likely to be seen with shapes that have well-defined corners than with shapes that have more curved features.
Therefore, there exists a need in the art for providing a method and structure that facilitates the assembly of microstructures within receptacles in a structure in a preferred orientation. There also exists a need in the art for providing a method and structure that facilities such assembly while avoiding the assembly of microstructures in a skewed manner that prevents proper seating of the microstructures.